AMD has further detailed its future Multi-Layer Chiplet Design technologies which are going to be integrated within next-generation processors such as the upcoming Zen 3 chips with 3D V-Cache technology.
AMD Talks Next-Gen Multi-Layer Chiplet Designs Featuring Hybrid 2D/2.5D & 3D Chiplet Technologies
The company talked about its existing chiplet designs and what the future holds in terms of multi-layer chip progression at HotChips 33. Currently, there are 14 package architectures for chiplets in development for various products that have already been released or coming out really soon. AMD states that the packaging choice and chiplet architecture depends on performance, power, area & the cost of the respective product (PPAC in short).
According to AMD, 2021 will mark the first introduction of its 3D Chiplet architecture design. We've already seen 2D and 2.5D packaging on consumer and server products but with 3D V-Cache, we are finally going to enter 3D chiplet stacking. The first product to feature this technology is going to be AMD's Zen 3 core which will feature an SRAM cache over the main Zen 3 CCD. The use of 3D chiplet technology also increases the interconnect density while staying in the lowest power and area. Few figures for the 3D V-Cache technology featured on Zen 3 CCD are listed here.
AMD has shared how it integrates the 3D V-Cache on top of its Zen 3 CCD. This is achieved through the use of Micro Bump (3D) and several TSV interconnects as mentioned above. The interconnect uses a brand new hydrophilic Dielectric-Dielectric Bonding with Direct CU-CU bonding which was designed and co-optimized in deep partnership with TSMC. The two individual silicons (chiplets) are bonded together using this technology.
According to AMD, the Hybrid bond has a 9u pitch and back-end similar to TSV which is slightly smaller than Intel's Forveros interconnect which has a 10u pitch. The interconnect energy efficiency is rated at higher than 3 times compared to Micron Bump 3D, the interconnect density is rated at more than 15 times higher than Micron Bump 3D and these 3D Chiplets also offer better signal/power thanks to lowering TSV capacitance, inductance.
AMD also highlights that DRAM on CPU is just the beginning of what they could achieve with 3D stacking. In the future, AMD expects to leverage 3D Stacking to stack cores on top of cores, IP on top of IP, and things get really crazy when Macroblocks could be 3D stacked on top of other Macro blocks.
The post AMD Discloses Its Multi-Layer Chiplet Design Era, Starting With Zen 3 With 3D Stacked V-Cache Technology by Hassan Mujtaba appeared first on Wccftech.
source https://wccftech.com/amd-discloses-multi-layer-chip-design-era-starting-with-zen-3-with-3d-stacked-v-cache-technology/
